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Preliminary Technical Data
FEATURES
Six Degrees of Freedom Inertial Sensor ADIS16385
FUNCTIONAL BLOCK DIAGRAM
AUX_ADC TEMPERATURE SENSOR TRI-AXIS MEMS ANGULAR RATE SENSOR CS SIGNAL CONDITIONING AND CONVERSION CALIBRATION AND DIGITAL PROCESSING OUTPUT REGISTERS AND SPI INTERFACE SCLK DIN DOUT AUX_DAC
Triaxis digital gyroscope with digital range scaling 75/sec, 150/sec, 300/sec settings Orthogonal alignment: <0.05 In-run bias stability: 6/hour (yaw), 25/hour (pitch/roll) Triaxis digital accelerometer: 5 g Autonomous operation and data collection No external configuration commands required Startup time: 180 ms Sleep mode recovery: 4 ms Factory-calibrated sensitivity, bias, and axial alignment Calibration temperature range: -40C to +85C Single serial peripheral interface, SPI-compatible Wide bandwidth: 330 Hz Embedded temperature sensor Programmable operation and control Automatic and manual bias correction controls Digital filters: Bartlett FIR, average/decimation Digital I/O: data-ready, alarm indicator, general-purpose Alarms for condition monitoring Sleep mode for power management DAC output voltage Enable external sample clock input: up to 1.2 kHz Single-supply operation: 4.85 V to 5.15 V 2000 g shock survivability Operating temperature range: -40C to +105C
TRI-AXIS MEMS ACCELERATION SENSOR ALARMS DIGITAL CONTROL POWER MANAGEMENT VCC
SELF-TEST
RST DIO1 DIO2 DIO3 DIO4/CLKIN
Figure 1.
GENERAL DESCRIPTION
The ADIS16385 iSensor(R) devices are complete inertial systems that include a triaxis gyroscope and triaxis accelerometer. Each sensor in the ADIS16385 combines industry-leading iMEMS(R) technology with signal conditioning that optimizes dynamic performance. The factory calibration characterizes each sensor for sensitivity, bias, alignment, and linear acceleration (gyro bias). As a result, each sensor has its own dynamic compensation formulas that provide accurate sensor measurements. The yaw-axis gyroscope offers a 4x improvement in noise and in-run bias stability for applications that have greater requirements on one axis. The ADIS16385 provide a simple, cost-effective method for integrating accurate, multiaxis inertial sensing into industrial systems, especially when compared with the complexity and investment associated with discrete designs. All necessary motion testing and calibration are part of the production process at the factory, greatly reducing system integration time. Tight orthogonal alignment simplifies inertial frame alignment in navigation systems. The SPI and register structure provide a simple interface for data collection and configuration control. The ADIS16385 has a compatible pinout for systems that currently use ADIS1635x, ADIS1636x, and ADIS1640x IMU products. It comes in a module that is approximately 36 mm x 47 mm x 39 mm and has a standard connector interface.
APPLICATIONS
Platform stabilization and control Navigation Robotics
Rev. PrA
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07570-001
ADIS16360/ ADIS16385 ADIS16365
GND
ADIS16385 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Timing Diagrams.......................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Basic Operation................................................................................. 9 Reading Sensor Data .................................................................... 9 Output Data Registers ................................................................ 10 Device Configuration ................................................................ 10 User Registers .................................................................................. 11 System Functions ............................................................................ 12 Global Commands ..................................................................... 12
Preliminary Technical Data
Power Management ................................................................... 12 Product Identification................................................................ 12 Memory Management ............................................................... 12 Self-Test Function ...................................................................... 13 Status ............................................................................................ 13 Input/Output Configuration ......................................................... 14 Data-Ready I/O Indicator ......................................................... 14 General-Purpose I/O ................................................................. 14 Auxiliary DAC ............................................................................ 14 Digital Processing Configuration ................................................. 15 Calibration ....................................................................................... 16 Alarms .............................................................................................. 17 Applications Information .............................................................. 18 Prototype Interface Board ......................................................... 18 Installation Tips .......................................................................... 18 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 19
Rev. PrA | Page 2 of 20
Preliminary Technical Data SPECIFICATIONS
TA = 25C, VCC = 5.0 V, angular rate = 0/sec, dynamic range = 300/sec 1 g, unless otherwise noted. Table 1.
Parameter GYROSCOPES Dynamic Range Initial Sensitivity Test Conditions/Comments Min 300 0.012375 Typ 350 0.0125 0.00625 0.003125 40 0.05 0.5 0.1 3 <0.002 0.007 <1.0 1.9 <0.01 0.01 <0.05 0.1 TBD 0.3 0.25 0.8 0.013 0.044 330 14.5 1400 Max
ADIS16385
Unit /sec /sec/LSB /sec/LSB /sec/LSB ppm/C Degrees Degrees % of FS /sec /sec /sec /hr /hr /sec/C /sec/C /sec/g /sec/g /sec/V /sec/V /sec rms /sec rms /sec/Hz rms /sec/Hz rms Hz kHz LSB g mg/LSB ppm/C Degrees Degrees % of FS mg g m/sec/hr mg/C mg/V mg rms mg/Hz rms Hz kHz LSB C/LSB
Sensitivity Temperature Coefficient Misalignment Nonlinearity Initial Bias Error In-Run Bias Stability Angular Random Walk Bias Temperature Coefficient Linear Acceleration Effect on Bias Bias Voltage Sensitivity Output Noise Rate Noise Density 3 dB Bandwidth Sensor Resonant Frequency Self-Test Change in Output Response ACCELEROMETERS Dynamic Range Initial Sensitivity Sensitivity Temperature Coefficient Misalignment Nonlinearity Initial Bias Error In-Run Bias Stability Velocity Random Walk Bias Temperature Coefficient Bias Voltage Sensitivity Output Noise Noise Density 3 dB Bandwidth Sensor Resonant Frequency Self-Test Change in Output Response TEMPERATURE SENSOR Scale Factor
Dynamic range = 300/sec Dynamic range = 150/sec Dynamic range = 75/sec -40C TA +85C Reference to z-axis accelerometer Axis-to-frame (package) Best fit straight line 1 1, +25C, Z-axis 1, +25C, X-axis, Y-axis Z-axis, 1 , +25C X-axis, Y-axis, 1 , +25C Z-axis, -40C TA +85C X, Y-axes, -40C TA +85C Z-axis, 1 (MSC_CTRL[7] = 1) X, Y-axes, 1 (MSC_CTRL[7] = 1) Z-axis, VCC = +4.85 V to +5.15V X, Y-axes, VCC = +4.85 V to +5.15V Z-axis, 300/sec range, no filtering X, Y-axes, 300/sec range, no filtering Z-axis, f = 25 Hz, 300/sec range X, Y-axes, f = 25 Hz, 300/sec range
0.12625
300/sec range setting Each axis
696 5 0.2475
2449
-40C TA +85C Axis-to-axis, = 90 ideal Axis-to-frame (package) Best fit straight line 1 1 1 -40C TA +85C VCC = +4.85 V to +5.15V No filtering No filtering
0.25 50 0.2 0.5 0.1 8 40 0.2 0.3 2.5 9 0.5 330 5.5
0.2525
X-axis and y-axis Output = 0x0000 at 25C (5C)
59 0.0678
151
Rev. PrA | Page 3 of 20
ADIS16385
Parameter ADC INPUT Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Input Range Input Capacitance DAC OUTPUT Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Output Range Output Impedance Output Settling Time LOGIC INPUTS1 Input High Voltage, VIH Input Low Voltage, VIL CS Wake-Up Pulse Width Logic 1 Input Current, IIH Logic 0 Input Current, IIL All Pins Except RST RST Pin Input Capacitance, CIN DIGITAL OUTPUTS1 Output High Voltage, VOH Output Low Voltage, VOL FLASH MEMORY Data Retention3 FUNCTIONAL TIMES4 Power-On Startup Time Reset Recovery Time Sleep Mode Recovery Time Flash Memory Test Time Automatic Self-Test Time CONVERSION RATE Clock Accuracy Sync Input Clock POWER SUPPLY Power Supply Current Test Conditions/Comments Min
Preliminary Technical Data
Typ 12 2 1 4 2 0 During acquisition 5 k/100 pF to GND 101 LSB input code 4095 LSB 20 12 4 1 5 0.5 0 2 10 2.0 CS signal to wake up from sleep mode 20 VIH = 3.3 V VIL = 0 V 0.2 40 1 10 ISOURCE = 1.6 mA ISINK = 1.6 mA Endurance2 TJ = 85C Time until data is available 2.4 0.4 10,000 20 TBD TBD TBD TBD TBD 1024 0.85 4.85 3 1.2 5.15 10 60 0.8 0.55 3.3 3.3 Max Unit Bits LSB LSB LSB LSB V pF Bits LSB LSB mV % V s V V V s A A mA pF V V Cycles Years ms ms ms ms ms SPS % kHz V mA A
SMPL_PRD = 0x0001 SMPL_PRD = 0x0001
Operating voltage range, VCC Sleep mode
5.0 TBD TBD
1 2
The digital I/O signals are driven by an internal 3.3 V supply, and the inputs are 5 V tolerant. Endurance is qualified as per JEDEC Standard 22, Method A117, and measured at -40C, +25C, +85C, and +125C. 3 The data retention lifetime equivalent is at a junction temperature (TJ) of 85C as per JEDEC Standard 22, Method A117. Data retention lifetime decreases with junction temperature. 4 These times do not include thermal settling and internal filter response times (330 Hz bandwidth), which may affect overall accuracy. 5 The sync input clock functions below the specified minimum value, at reduced performance levels.
Rev. PrA | Page 4 of 20
Preliminary Technical Data
TIMING SPECIFICATIONS
TA = 25C, VCC = 5 V, unless otherwise noted. Table 2.
Parameter fSCLK tSTALL tREADRATE tCS tDAV tDSU tDHD tSCLKR, tSCLKF tDR, tDF tSFS t1 tx t2 t3
1
ADIS16385
Description Serial clock Stall period between data Read rate Chip select to clock edge DOUT valid after SCLK edge DIN setup time before SCLK rising edge DIN hold time after SCLK rising edge SCLK rise/fall times DOUT rise/fall times CS high after SCLK edge Input sync positive pulse width Input sync low time Input sync to data ready output Input sync period
Min1 0.01 9 40 48.8 24.4 48.8
Normal Mode Typ Max 2.0
Min1 0.01 1/fSCLK 48.8
Burst Read Typ Max 1.0
100 24.4 48.8 5 5 5 5 100 600 833 833 12.5 12.5 5 5 100 600 5 5
100
12.5 12.5
Unit MHz s s ns ns ns ns ns ns ns s s s s
Guaranteed by design and characterization, but not tested in production.
TIMING DIAGRAMS
CS
tCS
1 SCLK 2 3 4 5 6 15 16
tSFS
tDAV
DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB
tDSU
DIN R/W A6 A5
tDHD
A4 A3 A2 D2 D1 LSB
07570-002
Figure 2. SPI Timing and Sequence
tREADRATE tSTALL
CS
07570-003
SCLK
Figure 3. Stall Time and Data Rate
t3 t2 t1
SYNC CLOCK (DIO4) DATA READY
07570-004
tX
Figure 4. Input Clock Timing Diagram
Rev. PrA | Page 5 of 20
ADIS16385 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Acceleration Any Axis, Unpowered Any Axis, Powered VCC to GND Digital Input Voltage to GND Digital Output Voltage to GND Analog Input to GND Operating Temperature Range Storage Temperature Range
1
Preliminary Technical Data
Rating 2000 g 2000 g -0.3 V to +7.0 V -0.3 V to +5.3 V -0.3 V to VCC + 0.3 V -0.3 V to +3.6 V -40C to +105C -65C to +125C1, 2
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4. Package Characteristics
Package Type 24-Lead Module (ML-24-5) JA JC Device Weight
Extended exposure to temperatures outside the specified temperature range of -40C to +105C can adversely affect the accuracy of the factory calibration. For best accuracy, store the parts within the specified operating range of -40C to +105C. 2 Although the device is capable of withstanding short-term exposure to 150C, long-term exposure threatens internal mechanical integrity.
ESD CAUTION
Rev. PrA | Page 6 of 20
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADIS16385
AUX_ADC
TOP VIEW (Not to Scale)
Z-AXIS
ADIS16385
aZ gZ
SCLK
DIO3
DIO1
DIO2
GND
GND
DNC
DNC
1
3
5
7
9
11
13
15
17
19
21
23
X-AXIS
DNC
VCC
DIN
2
4
6
8
10
12
14
16
18
20
22
24
Y-AXIS
DIO4/CLKIN
DOUT
GND
VCC
VCC
RST
CS
DNC
DNC
DNC
AUX_DAC
DNC
aY gY
PIN 23 PIN 1
aX gX
Figure 5. Pin Configuration
08562-005
NOTES 1. THIS REPRESENTATION DISPLAYS THE TOP VIEW PINOUT FOR THE MATING SOCKET CONNECTOR. 2. THE ACTUAL CONNECTOR PINS ARE NOT VISIBLE FROM THE TOP VIEW. 3. MATING CONNECTOR: SAMTEC CLM-112-02 OR EQUIVALENT. 4. DNC = DO NOT CONNECT.
ORIGIN ALIGNMENT REFERENCE POINT SEE MSC_CTRL[6]. NOTES 1. ACCELERATION (aX, aY, aZ) AND ROTATIONAL (gX, gY, gZ) ARROWS INDICATE THE DIRECTION OF MOTION THAT PRODUCES A POSITIVE OUTPUT.
Figure 6. Axial Orientation
Table 5. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7, 9 8 10, 11, 12 13, 14, 15 16, 17, 18, 19, 22, 23, 24 20 21
1
Mnemonic DIO3 DIO4/CLKIN SCLK DOUT DIN CS DIO1, DIO2 RST VCC GND DNC AUX_DAC AUX_ADC
Type1 I/O I/O I O I I I/O I S S N/A O I
Description Configurable Digital Input/Output. Configurable Digital Input/Output or Sync Clock Input. SPI Serial Clock. SPI Data Output. Clocks output on SCLK falling edge. SPI Data Input. Clocks input on SCLK rising edge. SPI Chip Select. Configurable Digital Input/Output. Reset. Power Supply. Power Ground. Do Not Connect. Auxiliary, 12-Bit DAC Output. Auxiliary, 12-Bit ADC Input.
I/O is input/output, I is input, O is output, S is supply, and N/A is not applicable.
Rev. PrA | Page 7 of 20
08562-006
ADIS16385 TYPICAL PERFORMANCE CHARACTERISTICS
ADIS16385 - Z GYRO Root Allan Variance 25C
Average=Solid; Dash=+/-1sigma
0.00100
Preliminary Technical Data
ADIS16385 - XL Root Allan Variance
Average=Solid; Dash=+/-1sigma
0.1000
Root Allan Variance [o/s]
Root Allan Variance [g]
0.0100
0.00010
0.0010
0.00001
1
10
100
Tau [sec]
1000
10000
1
10
100
Tau [sec]
1000
10000
Figure 7. Gyroscope Allan Variance, Z Axis
Figure 9. Accelerometer Allan Variance
ADIS16385 - XY GYRO Root Allan Variance 25C
Average=Solid; Dash=+/-1sigma
0.1000
Root Allan Variance [o/s]
0.0100
0.0010
1
10
100
Tau [sec]
1000
10000
Figure 8. Gyroscope Allan Variance, X-Axis/Y-Axis
Rev. PrA | Page 8 of 20
Preliminary Technical Data BASIC OPERATION
The ADIS16385 is an autonomous system that requires no user initialization. When it has a valid power supply, it initializes itself and starts sampling, processing, and loading sensor data into the output registers at a sample rate of 1024 SPS. DIO1 pulses high after each sample cycle concludes. The SPI interface enables simple integration with many embedded processor platforms, as shown in Figure 10 (electrical connection) and Table 6 (pin descriptions).
VDD I/O LINES ARE COMPATIBLE WITH 3.3V OR 5V LOGIC LEVELS
10
ADIS16385
READING SENSOR DATA
The ADIS16385 provides two different options for acquiring sensor data: single register and burst register. A single register read requires two 16-bit SPI cycles. The first cycle requests the contents of a register using the bit assignments in Figure 14. Bit DC7 to Bit DC0 are don't care for a read, and then the output register contents follow on DOUT during the second sequence. Figure 11 includes three single register reads in succession. In this example, the process starts with DIN = 0x0400 to request the contents of XGYRO_OUT, and follows with 0x0600 to request YGYRO_OUT, and 0x0800 to request ZGYRO_OUT. Full duplex operation enables processors to use the same 16-bit SPI cycle to read data from DOUT while requesting the next set of data on DIN. Figure 12 provides an example of the four SPI signals when reading XGYRO_OUT in a repeating pattern.
5V
11
12
SYSTEM PROCESSOR SPI MASTER
SS SCLK MOSI MISO IRQ
6 3 5 4 7
CS SCLK DIN DOUT DIO1
13
ADIS16385 ADIS16360/ ADIS16365
SPI SLAVE
14
15
07570-009
Figure 11. SPI Read Example
Figure 10. Electrical Connection Diagram
Table 6. Generic Master Processor Pin Names and Functions
Pin Name SS SCLK MOSI MISO IRQ Function Slave select Serial clock Master output, slave input Master input, slave output Interrupt request
Figure 12. Example SPI Read, Second 16-Bit Sequence
The ADIS16385 SPI interface supports full duplex serial communication (simultaneous transmit and receive) and uses the bit sequence shown in Figure 14. Table 7 provides a list of the most common settings that require attention to initialize a processor's serial port for the ADIS16385 SPI interface. Table 7. Generic Master Processor SPI Settings
Processor Setting Master SCLK Rate 2 MHz1 SPI Mode 3 MSB First Mode 16-Bit Mode
1
Burst-Read Function
The burst-read function enables the user to read all output registers using one command on the DIN line and shortens the stall time between each 16-bit segment to 1 SCLK cycle (see Table 2). Figure 13 provides the burst-read sequence of data on each SPI signal. The sequence starts with writing 0x3E00 to DIN, followed by each output register clocking out on DOUT, in the order in which they appear in Table 8.
Description The ADIS16385 operates as a slave Maximum serial clock rate CPOL = 1 (polarity), CPHA = 1 (phase) Bit sequence Shift register/data length
For burst read, SCLK rate 1 MHz. For low power mode, SCLK rate 300 kHz.
Figure 13. Burst-Read Sequence
CS SCLK DIN DOUT R/W D15 A6 D14 A5 D13 A4 D12 A3 D11 A2 D10 A1 D9 A0 D8 DC7 D7 DC6 D6 DC5 D5 DC4 D4 DC3 D3 DC2 D2 DC1 D1 DC0 D0 R/W D15 A6 D14 A5 D13
07570-011
NOTES 1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0.
Figure 14. SPI Communication Bit Sequence
Rev. PrA | Page 9 of 20
ADIS16385
OUTPUT DATA REGISTERS
The output registers in Table 8 provide the most recent sensor data produced by the ADIS16385. All of the inertial sensor outputs use a 16-bit, twos complement, data format. Figure 6 provides arrows that describe the direction of motion, which produces a positive output in each inertial sensor's output data register. Table 8. Output Data Register Formats
Register XGYRO_OUT1 YGYRO_OUT1 ZGYRO_OUT1 XACCL_OUT YACCL_OUT ZACCL_OUT TEMP_OUT2 AUX_ADC
1 2
Preliminary Technical Data
Table 12. Analog Input, Offset Binary Format
Input Voltage 3.3 V 1V 1.6116 mV 805.9 V 0V Decimal 4095 1241 2 1 0 Hex 0xFFF 0x4D9 0x002 0x001 0x000 Binary XXXX 1111 1111 1111 XXXX 0100 1101 1001 XXXX 0000 0000 0010 XXXX 0000 0000 0001 XXXX 0000 0000 0000
DEVICE CONFIGURATION
Format Table 9 Table 9 Table 9 Table 10 Table 10 Table 10 Table 11 Table 12
Address 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x10 0x12
Measurement Gyroscope, x-axis Gyroscope, y-axis Gyroscope, z-axis Accelerometer, x-axis Accelerometer, y-axis Accelerometer, z-axis Internal Temperature Auxiliary ADC
The control registers in Table 13 provide users with a variety of configuration options. The SPI provides access to these registers, one byte at a time, using the bit assignments in Figure 14. Each register has 16-bits, where bits [7:0] represent the lower address and Bits[15:8] represent the upper address. Figure 15 provides an example of writing 0x03 to Address 0x36 (SMPL_PRD[15:8]), using DIN = 0xB703. This example reduces the sample rate by a factor of eight (see Table 28).
Assumes that the scaling is set to 300/sec. This factor scales with the range. This is most useful for monitoring relative changes in the temperature.
Table 9. Rotation Rate, Twos Complement Format
Rotation Rate +300/sec +0.025/sec +0.0125/sec 0/sec -0.0125/sec -0.025/sec -300/sec Decimal +24000 +2 +1 0 -1 -2 -24000 Hex 0x5DC0 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0xA240 Binary 0101 1101 1100 0000 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1010 0010 0100 0000
Figure 15. Example SPI Write Sequence
Dual Memory Structure
Writing configuration data to a control register updates its SRAM contents, which are volatile. After optimizing each relevant control register setting in a system, set GLOB[12] = 1 (DIN = 0xBF10) to back these settings up in nonvolatile flash memory. The flash backup process requires a valid power supply level for the entire 75 ms process time. Table 13 provides a user register memory map that includes a flash back-up column. A yes in this column indicates that a register has a mirror location in flash, and when backed up properly, it automatically restores itself during start-up or after a reset. Figure 16 provides a diagram of the dual-memory structure used to manage operation and store critical user settings.
Table 10. Acceleration, Twos Complement Format
Acceleration +5 g +0.5 mg +0.25 mg 0g -0.25 mg -0.5 mg -5 g Decimal +20000 +2 +1 0 -1 -2 - 20000 Hex 0x4E20 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0xB1E0 Binary 0100 1110 0010 0000 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1011 0001 1110 0000
MANUAL FLASH BACKUP NONVOLATILE FLASH MEMORY (NO SPI ACCESS) START-UP RESET VOLATILE SRAM SPI ACCESS
07980-109
Table 11. Temperature, Twos Complement Format
Temperature +105C +25.1356C +25.0678C +25C +24.9322C +24. 8644C -40C Decimal +1180 +2 +1 0 -1 -2 -959 Hex 0x49C 0x002 0x001 0x000 0xFFF 0xFFE 0xC41 Binary XXXX 0100 1001 1100 XXXX 0000 0000 0010 XXXX 0000 0000 0001 XXXX 0000 0000 0000 XXXX 1111 1111 1111 XXXX 1111 1111 1110 XXXX 1100 0100 0001
Figure 16. SRAM and Flash Memory Diagram
Rev. PrA | Page 10 of 20
Preliminary Technical Data USER REGISTERS
Table 13. User Register Memory Map1
Name FLASH_CNT Reserved XGYRO_OUT YGYRO_OUT ZGYRO_OUT XACCL_OUT YACCL_OUT ZACCL_OUT TEMP_OUT AUX_ADC Reserved XGYRO_OFF YGYRO_OFF ZGYRO_OFF XACCL_OFF YACCL_OFF ZACCL_OFF ALM_MAG1 ALM_MAG2 ALM_SMPL1 ALM_SMPL2 ALM_CTRL AUX_DAC GPIO_CTRL MSC_CTRL SMPL_PRD SENS_AVG SLP_CTRL DIAG_STAT GLOB_CMD Reserved LOT_ID1 LOT_ID2 PROD_ID SERIAL_NUM
1 2
ADIS16385
R/W R N/A R R R R R R R R N/A R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R R/W N/A R R R R
Flash Backup Yes N/A No No No No No No No No N/A Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Yes No No No N/A Yes Yes Yes Yes
Address2 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x10 0x12 0x014 to 0x19 0x1A 0x1C 0x1E 0x20 0x22 0x24 0x26 0x28 0x2A 0x2C 0x2E 0x30 0x32 0x34 0x36 0x38 0x3A 0x3C 0x3E 0x40 to 0x51 0x52 0x54 0x56 0x58
Default N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0006 0x0001 0x0402 0x0000 0x0000 0x0000 N/A N/A N/A 0x4001 N/A
Register Description Flash memory write count Reserved X-axis gyroscope output Y-axis gyroscope output Z-axis gyroscope output X-axis accelerometer output Y-axis accelerometer output Z-axis accelerometer output Internal temperature output Auxiliary ADC output Reserved X-axis gyroscope bias correction factor Y-axis gyroscope bias correction factor Z-axis gyroscope bias correction factor X-axis acceleration bias correction factor Y-axis acceleration bias correction factor Z-axis acceleration bias correction factor Alarm 1, amplitude threshold Alarm 2, amplitude threshold Alarm 1, dynamic time change Alarm 2, dynamic time change Alarm control Auxiliary DAC output level setting Auxiliary digital input/output control Miscellaneous control: data ready, self-test Sample clock source, decimation rate Dynamic range and digital filter control Sleep mode control System status (error flags) System command (global) Reserved Lot Identification Code 1 Lot Identification Code 2 Product identification, ADIS16385 Serial number
Reference Table 20 N/A Table 9 Table 9 Table 9 Table 10 Table 10 Table 10 Table 11 Table 12 Table 31 Table 31 Table 31 Table 32 Table 32 Table 32 Table 34 Table 35 Table 36 Table 36 Table 37 Table 25 Table 24 Table 21 Table 28 Table 29 Table 16 Table 22 Table 15 Table 17 Table 17 Table 19 Table 18
N/A = not applicable. Each register contains two bytes. The address of the lower byte is displayed. The address of the upper byte is equal to the address of the lower byte plus 1.
Rev. PrA | Page 11 of 20
ADIS16385 SYSTEM FUNCTIONS
The ADIS16385 provides a number of system-level controls for managing its operation, using the registers in Table 14. Table 14. System Tool Registers
Register Name MSC_CTRL SLP_CTRL DIAG_STAT GLOB_CMD LOT_ID1 LOT_ID2 PROD_ID SERIAL_NUM Address 0x34 0x3A 0x3C 0x3E 0x52 0x54 0x56 0x58 Description Self-test, calibration, data-ready Sleep mode control Error flags Single-command functions Lot Identification Code 1 Lot Identification Code 2 Product identification: Serial number
Preliminary Technical Data
Table 16. SLP_CTRL Bit Descriptions
Bits [15:9] [8] [7:0] Description (Default = 0x0000) Not used Normal sleep mode, (1 = start sleep mode) Timed sleep mode (write 0x01 to 0xFF to start). Sleep mode duration, binary, 0.5 sec/LSB
PRODUCT IDENTIFICATION
The PROD_ID register in Table 19 contains the binary equivalent of 16,385. It provides a product-specific variable for systems that need to track this in their system software. The LOT_ID1 and LOT_ID2 registers in Table 17 combine to provide a unique, 32-bit lot identification code. The SERIAL_NUM register in Table 18 contains a binary number that represents the serial number on the device label. The assigned serial numbers in SERIAL_NUM are lot specific. Table 17. LOT_ID1, LOT_ID2 Bit Descriptions
Bits [15:0] Description (Default = 0x0000) Lot identification, binary code
GLOBAL COMMANDS
The GLOB_CMD register in Table 15 provides trigger bits for device reset, flash memory management, DAC control, and calibration control. Start each of these functions by writing a 1 to the assigned bit in GLOB_CMD. After completing the task, the bit automatically returns to zero. For example, set GLOB_CMD[7] = 1 (DIN = 0xBE80) to initiate a software reset, which stops the sensor operation and runs the device through its startup sequence. Set GLOB_CMD[3] = 1 (DIN = 0xBE04) to back up the user register contents in nonvolatile flash. This sequence includes loading the control registers with the data in their respective flash memory locations prior to producing new data. Table 15. GLOB_CMD Bit Descriptions
Bits [15:8] [7] [6:4] [3] [2] [1] [0]
1 2
Table 18. SERIAL_NUM Bit Descriptions
Bits [15:14] [13:0] Description (Default = 0x0000) Reserved Serial number, 1 to 9999 (0x270F)
Table 19. PROD_ID Bit Descriptions
Execution Time N/A 4 ms N/A 75 ms 75 ms 75 ms N/A2
1
Description (Default = 0x0000) Not used Software reset Not used Flash update Auxiliary DAC data latch Factory calibration restore Automatic bias correction
Bits [15:0]
Description (Default = 0x0000) Product identification = 0x4001
MEMORY MANAGEMENT
The FLASH_CNT register in Table 20 provides a 16-bit counter that helps track the number of write cycles to the nonvolatile flash memory. The flash updates every time any of the following bits are set to 1: GLOB_CMD[3] and GLOB[1:0]. Table 20. FLASH_CNT Bit Descriptions
Bits [15:0] Description Binary counter
N/A = not applicable. Execution time is dependent on SMPL_PRD[12:8] setting.
POWER MANAGEMENT
The SLP_CTRL register, in Table 16, provides two different sleep modes for system-level management: normal and timed. Set SLP_CTRL[8] = 1 (DIN = 0xBB01) to start normal sleep mode. When the device is in sleep mode, the following events can cause it to wake-up: assert CS from high to low, assert RST from high to low, or cycle the power. Use SLP_CTRL[7:0] to put the device into sleep mode for a specified period. For example, SLP_CNT[7:0] = 0x64 (DIN = 0xBA64) puts the ADIS16385 to sleep for 50 sec.
Rev. PrA | Page 12 of 20
Preliminary Technical Data
Checksum Test
Set MSC_CTRL[6] = 1 (DIN = 0xB508) to perform a checksum verification of the internal program memory. This takes a summation of the internal program memory and compares it with the original summation value for the same locations (from factory configuration). Check the results in the DIAG_STAT register, which is in Table 22. DIAG_STAT[6] equals 0 if the sum matches the correct value and 1 if it does not. Make sure that the power supply is within specification for the entire 20 ms that this function takes to complete.
ADIS16385
There are two self-test options in the MSC-CTRL register: internal and manual. Set MSC_CTRL[10] = 1 (DIN = 0xB504) to run the internal self-test routine, which exercises all inertial sensors, measures each response, computes the response to the self-test stimulus, makes pass/fail decisions, and reports them to the error flags in DIAG_STAT[5] and DIAG_STAT[15:10]. While DIAG_STAT[15:10] provide individual error flags for each inertial sensor, DIAG_STAT[5] provides a single-bit for indicating a failure in any of the inertial sensors. MSC_CTRL[10] resets itself to 0 after completing the routine. Set MSC_CTRL[8] = 1 (DIN = B501) to manually activate the self-test function on all six sensors. Set MSC_CTRL[8] = 0 (DIN = B500) to manually de-activate the self-test function on all six sensors. Measure the output bias for each MSC_CTRL[8] setting (0 and 1), take the difference between them, and compare this difference with the expected self-test response in Table 1.
SELF-TEST FUNCTION
The MSC_CTRL register in Table 21 provides a self-test function for all six MEMS inertial sensors. This function allows the user to verify the mechanical integrity of each MEMS sensor. When enabled, the self-test applies an electrostatic force to each internal sensor element, which causes them to move. The movement in each element simulates its response to actual rotation/acceleration and generates a predictable electrical response in the sensor outputs. Table 1 provides the expected response for both gyroscopes and accelerometers that can help establish pass/fail limits during system-level diagnostic testing. Table 21. MSC_CTRL Bit Descriptions
Bits [15:12] [11] [10] [9] [8] [7] [6] [5:3] [2] [1] [0]
1
STATUS
The DIAG_STAT register in Table 22 provides error flags for a number of functions. Each flag uses 1 to indicate an error condition and 0 to indicate a normal condition. Reading this register provides access to each flag's status and resets all of the bits to 0 for monitoring future operation. If the error condition remains, the error flag will return to 1 at the conclusion of the next sample cycle. DIAG_STAT[0] does not require a read of this register to return to 0. If the power supply voltage goes back into range, this flag clears automatically. The SPI communication error flag in DIAG_STAT[3] indicates that the number of SCLKs in a SPI sequence did not equal a multiple of 16 SCLKs. Table 22. DIAG_STAT Bit Descriptions
Bits [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Description (Default = 0x0000) Z-axis accelerometer self-test failure (1 = fail, 0 = pass) Y-axis accelerometer self-test failure (1 = fail, 0 = pass) X-axis accelerometer self-test failure (1 = fail, 0 = pass) Z-axis gyroscope self-test failure (1 = fail, 0 = pass) Y-axis gyroscope self-test failure (1 = fail, 0 = pass) X-axis gyroscope self-test failure (1 = fail, 0 = pass) Alarm 2 status (1 = active, 0 = inactive) Alarm 1 status (1 = active, 0 = inactive) Not used Flash test, checksum flag (1 = fail, 0 = pass) Self-test diagnostic error flag (1 = fail, 0 = pass) Sensor over-range (1 = over-range, 0 = normal) SPI communication failure (1 = fail, 0 = pass) Flash update failure (1 = fail, 0 = pass) Not used Power supply low, (1 = VDD <4.85V, 0 = VDD 4.85V)
Description (Default = 0x0006) Not used Memory test (cleared upon completion)1 (1 = enabled, 0 = disabled) Internal self-test (cleared upon completion)1 (1 = enabled, 0 = disabled) Not used Manual self-test (1 = enabled, 0 = disabled) Linear acceleration bias compensation for gyroscopes (1 = enabled, 0 = disabled) Point of percussion, per Figure 6 (1 = enabled, 0 = disabled) Not used Data-ready enable (1 = enabled, 0 = disabled) Data-ready polarity (1 = active high, 0 = active low) Data-ready line select (1 = DIO2, 0 = DIO1)
The bit automatically restores to zero after finishing the test
Rev. PrA | Page 13 of 20
ADIS16385 INPUT/OUTPUT CONFIGURATION
Table 23 provides a summary of registers that provide input/output configuration and control. Table 23. Input/Output Registers
Register Name AUX_DAC GPIO_CTRL MSC_CTRL Address 0x30 0x32 0x34 Description Output voltage control, AUX_DAC General-purpose I/O control Self-test, calibration, data-ready
Preliminary Technical Data
Example I/O Configuration
For example, set GPIO_CTRL[3:0] = 0100 to set DIO3 as an output signal pin and DIO1, DIO2, and DIO4 as input signal pins. Set the output on DIO3 to 1 by setting GPIO_CTRL[10] = 1 (DIN = 0xB304). Then, read GPIO_CTRL (DIN = 0x3200) and mask off GPIO_CTRL[9:8] and GPIO_CTRL[11] to monitor the digital signal levels on DIO4, DIO2, and DIO1.
AUXILIARY DAC DATA-READY I/O INDICATOR
The factory-default setting of MSC_CTRL[2:0] (110) establishes DIO1 as a positive-polarity data-ready signal. See Table 21 for additional data-ready configuration options. For example, set MSC_CTRL[2:0] = 100 (DIN = 0xB404) to change the polarity of the data-ready signal on DIO1 for interrupt inputs that require negative logic inputs for activation. The pulse width is between 100 s and 200 s over all conditions. The AUX_DAC register in Table 25 provides user controls for setting the output voltage on the AUX_DAC pin. The 12-bit AUX_DAC line can drive its output to within 5 mV of the ground reference when it is not sinking current. As the output approaches 0 V, the linearity begins to degrade (~100 LSB starting point). As the sink current increases, the nonlinear range increases. The DAC latch command in GLOB_CMD[2] (see Table 15) moves the values of the AUX_DAC register into the DAC input register, enabling both bytes to take effect at the same time. This prevents undesirable output levels, which reflect single-byte changes of the AUX_DAC register. Table 25. AUX_DAC Bit Descriptions
Bits [15:12] [11:0] Description (Default = 0x0000) Not used Data bits, scale factor = 0.8059 mV/LSB Offset binary format, 0 V = 0 LSB
GENERAL-PURPOSE I/O
DIO1, DIO2, DIO3, and DIO4 are configurable, general-purpose I/O lines that serve multiple purposes. The data-ready controls in MSC_CTRL[2:0] have the highest priority for configuring DIO1 and DIO2. The alarm indicator controls in ALM_CTRL[2:0] have the second-highest priority for DIO1 and DIO2. GPIO_CTRL in Table 24 has the lowest priority for configuration DIO1, DIO2, and DIO4 and has absolute control over DIO3. Table 24. GPIO_CTRL Bit Descriptions
Bits [15:12] [11] [10] [9] [8] [7:4] [3] [2] [1] [0] Description (Default = 0x0000) Not used General-Purpose I/O Line 4 (DIO4) data level General-Purpose I/O Line 3 (DIO3) data level General-Purpose I/O Line 2 (DIO2) data level General-Purpose I/O Line 1 (DIO1) data level Not used General-Purpose I/O Line 4 (DIO4) direction control (1 = output, 0 = input) General-Purpose I/O Line 3 (DIO3) direction control (1 = output, 0 = input) General-Purpose I/O Line 2 (DIO2) direction control (1 = output, 0 = input) General-Purpose I/O Line 1 (DIO1) direction control (1 = output, 0 = input)
Table 26. Setting AUX_DAC = 1 V
DIN 0xB0D9 0xB104 0xBE04 Description AUX_DAC[7:0] = 0xD9 (217 LSB) AUX_DAC[15:8] = 0x04 (1024 LSB) GLOB_CMD[2] = 1; move values into the DAC input register, resulting in a 1 V output level
Rev. PrA | Page 14 of 20
Preliminary Technical Data DIGITAL PROCESSING CONFIGURATION
Table 27. Digital Processing Registers
Register Name SMPL_PRD SENS_AVG Address 0x36 0x38 Description Sample rate control Digital filtering and range control
0 -20 -40
MAGNITUDE (dB)
ADIS16385
Sample Rate
The internal sampling system produces new data in the output data registers at a rate of 1024 SPS. The SMPL_PRD register in Table 28 provides two functional controls that affect sampling and register update rates. SMPL_PRD[12:8] provides a control for reducing the update rate, using an averaging filter with a decimated output. These bits provide a binomial control that divides the data rate by a factor of 2 every time this number increases by one. For example, set SMPL_PRD[12:8] = 0100 (DIN = 0xB704) to set the decimation factor to 16. This reduces the update rate to 64 SPS and the bandwidth to 31 Hz. Table 28. SMPL_PRD Bit Descriptions
Bits [15:13] [12:8] [7:1] [0] Description (Default = 0x0001) Not used Average/decimation rate setting, binomial Not used Clock: 1 = internal (1024 SPS), 0 = external
-60 -80 -100 -120 -140 0.001 N=2 N=4 N = 16 N = 64 0.01 0.1 1
07570-014
FREQUENCY (f/fS)
Figure 17. Bartlett Window, FIR Filter Frequency Response (Phase Delay = N Samples)
Dynamic Range
The SENS_AVG[10:8] bits provide three dynamic range settings for this gyroscope. The lower dynamic range settings (75/sec and 150/sec) limit the minimum filter tap sizes to maintain resolution. For example, set SENS_AVG[10:8] = 010 (DIN = 0xB902) for a measurement range of 150/sec. Because this setting can influence the filter settings, program SENS_AVG[10:8] before programming SENS_AVG[2:0] if more filtering is required. Table 29. SENS_AVG Bit Descriptions
Bits [15:11] [10:8] Description (Default = 0x0402) Not used Measurement range (sensitivity) selection 100 = 300/sec (default condition) 010 = 150/sec, filter taps 4 (Bits[2:0] 0x02) 001 = 75/sec, filter taps 16 (Bits[2:0] 0x04) Not used Number of taps in each stage; value of m in N = 2m
Input Clock Configuration
SMPL_PRD[0] provides a control for synchronizing the internal sampling to an external clock source. Set GPIO_CTRL[3] = 0 (DIN = 0x0B200) and SMPL_PRD[0] = 0 (DIN = 0xB600) to enable the external clock. See Table 2 and Figure 4 for timing information.
Digital Filtering
The SENS_AVG register in Table 29 provides user controls for the low-pass filter. This filter contains two cascaded averaging filters that provide a Bartlett window, FIR filter response (see Figure 18). For example, set SENS_AVG[2:0] = 100 (DIN = 0xB804) to set each stage to 16 taps. When used with the default sample rate of 1024 SPS and zero decimation (SMPL_PRD[12:8] = 00000), this value reduces the sensor bandwidth to approximately 20 Hz.
[7:3] [2:0]
1 NB
x(n)
n =1
NB
1 NB
x(n)
n =1
NB
1 ND
x(n)
n =1
ND
/ ND
B = SENS_AVG[2 : 0] N B = 2B N B = Number of taps (per stage)
D = SMPL_PRD[12 : 8] N D = 2D N D = Number of taps
Figure 18. Sampling and Frequency Response Block Diagram
Rev. PrA | Page 15 of 20
ADIS16385 CALIBRATION
The mechanical structure and assembly process of the ADIS16385 provide excellent position and alignment stability for each sensor, even after subjected to temperature cycles, shock, vibration, and other environmental conditions. The factory calibration includes a dynamic characterization of each sensor's behavior over temperature and generates sensor-specific correction formulas. The bias correction registers in Table 30 provide users with the ability to address bias shifts that can result from mechanical stress. Figure 19 illustrates the summing function of each sensor's offset correction register. Table 30. Registers for User Calibration
Register XGYRO_OFF YGYRO_OFF ZGYRO_OFF XACCL_OFF YACCL_OFF ZACCL_OFF GLOB_CMD Address 0x1A 0x1C 0x1E 0x20 0x22 0x24 0x3E Description Gyroscope bias, x-axis Gyroscope bias, y-axis Gyroscope bias, z-axis Accelerometer bias, x-axis Accelerometer bias, y-axis Accelerometer bias, z-axis Automatic calibration
Preliminary Technical Data
ABC Example
Set SMPL_PRD[15:8] = 0x10 (DIN = 0xB710) to set the decimation rate to 65,536 (216), which provides an averaging time of 64 seconds (65536 / 1024 SPS) for this function. Then, set GLOB_CMD[0] = 1 (DIN = 0xBE01) and keep the platform stable for at least 65 seconds while the gyroscope bias data accumulates. After this completes, the ADIS16385 automatically updates the flash memory. The SPI is inactive and does not respond to user inputs while the ABC is processing. The only way to interrupt it is to remove power or initiate a hardware reset using the RST pin. When using SMPL_PRD[12:8] = 0x10, the 1- accuracy for this correction is approximately 0.008/sec for the X-axis and Y-axis gyroscopes and 0.003/sec for the Z-axis gyroscope. See Table 15 for more information on GLOB_CMD.
Manual Bias Correction
The manual bias correction (MBC) function requires the user to collect the desired number of samples, calculate the averages to develop bias estimates for each gyroscope channel, and then write them into the bias offset registers, located in Table 31 for the gyroscopes. For example, set XGYRO_OFF = 0x1FF6 (DIN = 0x9B1F, 0x9AF6) to adjust the XGYRO_OUT offset by -0.03125/sec (-10 LSBs). Table 32 provides a manual adjustment function for the accelerometer channels as well. Table 31. XGYRO_OFF, YGYRO_OFF, and ZGYRO_OFF Bit Descriptions
Figure 19. User Calibration, XGYRO_OFF Example
There are two options for optimizing gyroscope bias accuracy prior to system deployment: automatic bias correction (ABC) and manual bias correction (MBC).
Bits [15:0]
Description (Default = 0x0000) Twos complement, 0.003125/sec per LSB. Typical adjustment range = 102/sec.
Automatic Bias Correction (ABC)
Set GLOB_CMD[0] = 1 (DIN = 0xBE01) to start the ABC function, which uses the following internal sequence to calibrate each gyroscope for bias error: 1. Set the output range to 75/sec and wait for a complete output data cycle to complete (the SMPL_PRD[12:8] bits set this time). Read the output register of the gyroscope. Multiply the measurement by -1 to change its polarity. Write the final value into the offset register.
Table 32. XACCL_OFF, YACCL_OFF, and ZACCL_OFF Bit Descriptions
Bits [15:0] Description (Default = 0x0000) Data bits. Twos complement, 0.25 mg/LSB. Typical adjustment range = 8.192 g.
Restoring Factory Calibration Set GLOB_CMD[1] = 1 (DIN = 0xBE02) to execute the factory calibration restore function. This is a single-command function, which resets each user calibration register to 0x0000 and all sensor data to zero. Then, it automatically updates the flash memory within 50 ms. See Table 15 for more information on GLOB_CMD.
2. 3. 4.
The Allan Variance curves in Figure 7, Figure 9, and Figure 8 provide a trade-off between bias accuracy and averaging time. SMPL_PRD[12:8] provide a user control for averaging time when using the ABC function. Use this setting, in combination with GLOB_CMD[0], to create the automatic bias correction function.
Point-of-Percussion (Gyroscope)
Set MSC_CTRL[6] = 1 (DIN = 0xB486) to enable this feature and maintain the factory-default settings for DIO1. This feature performs a point-of-percussion translation to the point identified in Figure 6. See Table 21 for more information on MSC_CTRL.
Rev. PrA | Page 16 of 20
Preliminary Technical Data ALARMS
The ADIS16385 provides two independent alarms, Alarm 1 and Alarm 2, which have a number of programmable settings. Table 33 provides a list of registers for these user settings. Table 33. Registers for Alarm Configuration
Register ALM_MAG1 ALM_MAG2 ALM_SMPL1 ALM_SMPL2 ALM_CTRL Address 0x26 0X28 0x2A 0x2C 0x2E Description Alarm 1, trigger setting Alarm 2, trigger setting Alarm 1, sample period Alarm 2, sample period Alarm configuration
ADIS16385
Table 37. ALM_CTRL Bit Descriptions
Bits [15:12] Description (Default = 0x0000) Alarm 2 data source selection 0000 = disable 0001 = x-axis gyroscope output 0010 = y-axis gyroscope output 0011 = z-axis gyroscope output 0100 = x-axis accelerometer output 0101 = y-axis accelerometer output 0110 = z-axis accelerometer output 0111 = internal temperature output 1000 = auxiliary ADC input 1001 = self test Alarm 1 data source selection (same as Alarm 2) Alarm 2, dynamic/static (1 = dynamic, 0 = static) Alarm 1, dynamic/static (1 = dynamic, 0 = static) Alarm 2, polarity (1 = greater than, 0 = less than) Alarm 1, polarity (1 = greater than, 0 = less than) Data source filtering (1 = filtered, 0 = unfiltered) Alarm indicator (1 = enabled, 0 = disabled) Alarm indicator active polarity (1 = high, 0 = low) Alarm output line select (1 = DIO2, 0 = DIO1)
The ALM_CTRL register in Table 37 provides data source selection (Bits[15:8]), static/dynamic setting for each alarm (Bits[7:6]), trigger polarity (Bits[5:4]), data source filtering (Bit[3]), and alarm indicator signal (Bits[2:0]).
Static Alarm Use
The static alarms setting compares the data source selection (ALM_CTRL[15:8]) with the values in the ALM_MAGx registers in Table 34 and Table 35. The data format in these registers matches the format of the data selection in ALM_CTRL[15:8]. The ALM_CTRL[5:4] bits provide polarity settings. See Table 38, Alarm 1, for a static alarm configuration example. Table 34. ALM_MAG1 Bit Descriptions
Bits [15:0] Description (Default = 0x0000) Threshold setting; matches for format of ALM_CTRL[11:8] selection
[11:8] [7] [6] [5] [4] [3] [2] [1] [0]
Alarm Example
Table 38 offers an example that configures Alarm 1 to trigger when filtered ZACCL_OUT data drops below 0.7g, and Alarm 2 to trigger when filtered ZGYRO_OUT data changes by more than 50/sec over a 100 ms period, or 5,000/sec2. The filter setting helps reduce false triggers from noise and refine the accuracy of the trigger points. The ALM_SMPL2 setting of 102 samples provides a comparison period that is 99.6 ms for an internal sample rate of 1024 SPS. Because Alarm 1 is a static alarm in this example, there is no need to program ALM_SMPL1. Table 38. Alarm Configuration Example 1
DIN 0xAF36, 0xAEAF Description ALM_CTRL = 0x36AF. Alarm 2: dynamic, -ZGYRO_OUT (-time, ALM_SMPL2) > ALM_MAG2. Alarm 1: static, ZACCL_OUT < ALM_MAG1. Use filtered data source for comparison. DIO2 output indicator, positive polarity. ALM_MAG2 = 0x0FA0 (+50/sec). ALM_MAG1 = 0x0AF0 (0.7 g). ALM_SMPL2[7:0] = 0x66 (102 samples).
Table 35. ALM_MAG2 Bit Descriptions
Bits [15:0] Description (Default = 0x0000) Threshold setting; matches for format of ALM_CTRL[15:12] selection
Dynamic Alarm Use
The dynamic alarm setting monitors the data selection for a rate-of-change comparison. The rate-of-change comparison is represented by the magnitude in the ALM_MAGx registers over the time represented by the number-of-samples setting in the ALM_SMPLx registers, located in Table 36. See Table 38, Alarm 2, for a dynamic alarm configuration example. Table 36. ALM_SMPL1 and ALM_SMPL2 Bit Descriptions
Bits [15:8] [7:0] Description (Default = 0x0000) Not used Binary, number of samples (both 0x00 and 0x01 = 1)
Alarm Reporting
The DIAG_STAT[9:8] bits provide error flags that indicate an alarm condition. The ALM_CTRL[2:0] bits provide controls for a hardware indicator using DIO1 or DIO2.
0xA90F, 0xA8A0 0xA70A, 0xA6F0 0xAC76
Rev. PrA | Page 17 of 20
ADIS16385 APPLICATIONS INFORMATION
PROTOTYPE INTERFACE BOARD
The ADIS16385/PCBZ includes one ADIS16385BMLZ, one interface printed circuit board (PCB), and four M2x18 machine screws. The interface PCB provides larger connectors than the ADIS16385BMLZ for simpler prototyping, four-tapped M2 holes for attachment of the ADIS16385BMLZ, and four holes (machine screw size M2.5 or #4) for mounting the ADIS16385BMLZ to a solid structure. J1 and J2 are dual-row, 2 mm (pitch) connectors that work with a number of ribbon cable systems, including 3M Part Number 152212-0100-GB (ribbon crimp connector) and 3M Part Number 3625/12 (ribbon cable). Figure 20 provides the top-level view of the interface board. Install the ADIS16385BMLZ onto this board using the silk pattern as an orientation guide. Figure 21 provides the pin assignments for J1 and J2. The pin descriptions match those listed in Table 5. The ADIS16385 does not require external capacitors for normal operation; therefore, the interface PCB does not use the C1/C2 pads.
Preliminary Technical Data
INSTALLATION TIPS
Figure 22 and Figure 23 provide the mechanical design information used for the ADIS16385/PCBZ. Use Figure 22 and Figure 23 when implementing a connector-down approach, where the mating connector and the ADIS16385BMLZ are on the same surface. When designing a connector-up system, use the mounting holes shown in Figure 22 as a guide in designing the bulkhead mounting system and use Figure 23 as a guide in developing the mating connector interface on a flexible circuit or other connector system.
31.200 BSC 15.600 BSC
39.60 BSC 19.800 BSC 17.520
2x 0.560 BSC ALIGNMENT HOLES FOR MATING SOCKET
2.280
iSensor
4x 2.500 BSC 5.00 BSC 5.00 BSC
08888-022
Figure 22. Suggested Mounting Hole Locations, Connector Down
0.4334 [11.0] 0.019685 [0.5000] (TYP) 0.0240 [0.610]
0.054 [1.37] 0.0394 [1.00] 0.1800 [4.57]
08888-020
Figure 20. Physical Diagram for the ADIS16385/PCBZ
J1 RST CS DNC GND GND VCC 1 3 5 7 9 11 2 4 6 8 10 12 SCLK DOUT DIN GND VCC VCC DNC DNC GND DNC DNC DIO2 1 3 5 7 9 11 J2 2 4 6 8 10 12 GND DNC CLKIN DNC DNC DIO1
08888-021
Figure 23. Suggested Layout and Mechanical Design for the Mating Connector
Figure 21. J1/J2 Pin Assignments
Rev. PrA | Page 18 of 20
08888-023
0.022 DIA (TYP) NONPLATED 0.022 DIA THRU HOLE (TYP) THRU HOLE 2x NONPLATED THRU HOLE
0.0394 [1.00]
Preliminary Technical Data OUTLINE DIMENSIONS
35.600 31.200 15.600 5.50 15.600 5.50
ADIS16385
19.800
17.520
44.000
47.186 2.40 THRU HOLE (4x)
2.200 (4x)
17.800
2.500 (RADIUS)
39.000 FRONT VIEW
BOTTOM VIEW
38.428
20.678 3.750 15.478
0.30 SQ BSC (24x)
1.00 BSC LEAD PITCH
SIDE VIEW
091609-A
47.186
Figure 24. 24-Lead Module with Connector Interface (ML-24-5) Dimensions shown in millimeters
ORDERING GUIDE
Model1 ADIS16385BMLZ ADIS16385/PCBZ
1
Temperature Range -40C to +105C
Package Description 24-Lead Module with Connector Interface Interface PCB
Package Option ML-24-5
Z = RoHS Compliant Part.
Rev. PrA | Page 19 of 20
ADIS16385 NOTES
Preliminary Technical Data
(c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR08562-0-6/10(PrA)
Rev. PrA | Page 20 of 20

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